1. Field of the Invention
The present invention relates to the field of operational and instrumentation amplifiers.
2. Prior Art
One of the key performance specifications of an operational amplifier is its DC error or offset voltage. The offset voltage limits the ability of the amplifier to resolve small DC input voltages. The total offset voltage is usually specified assuming a single source of error at the input terminals. The value of this imaginary voltage source represents the input referred offset voltage of the amplifier. The significance of this parameter lies in the fact that the amplifier will not be able to resolve any DC voltages at its input that are smaller than the input referred offset voltage.
In monolithically integrated operational amplifiers, the input referred offset voltage (also called input offset, offset voltage or just offset for short) is mostly due to statistical mismatch between critical components in the circuit. Commonly, these critical components include the input stage transistors, but other devices may contribute significantly to the offset as well. Typical offset voltages due to component mismatch lay in the order of several millivolts.
A well-known technique to reduce the input referred offset voltage of an amplifier is by trimming each amplifier during manufacturing. At some stage in the production process—usually while electrically screening the parts for defects—the native offset of the part is measured, and corresponding modifications are made to the part to compensate for this offset. The modifications to the part need to be permanent, in order for the offset to remain compensated for over the life of the product.
Many techniques have been proposed and used in the past to make permanent changes to an IC in order to store the offset compensation voltage. Examples include trimming resistors with a laser, blowing links with a laser, shorting out zener diodes by a high reverse voltage, blowing metal fuses with a high current, modifying the resistivity of a poly-silicon resistor with a high current and storing digital bits onto a non-volatile memory (e.g. flash).
Based on the timing of the trimming during the production process, all trimming techniques can be classified into one of two categories:
1. pre-package trim
2. post-package trim
As the name implies, pre-package trim includes all trim techniques that take place before the silicon die is packaged into its final package. Reversely, post-package trim is done after packaging the part.
The distinction between pre and post-package trim is a critical one, since the packaging process can lead to significant offset shifts of the part. Especially plastic packages, which include the majority of all parts being shipped today, can inflict high mechanical stresses to the silicon die. The piezoelectric properties of silicon convert the mechanical stresses into offset voltage shifts of the circuit. These offset shifts in their turn cause the input referred offset voltage of the part to change randomly after packaging. Typical offset shifts due to packaging are on the order of several 100 s of microvolts.
A part that was trimmed for zero offset before packaging (pre-package trim), will most likely show a non-zero offset after being assembled. Therefore, pre-package trim is not able to guarantee very high accuracies of the trimmed offset voltage.
Post-package trim, on the other hand, takes into account offset shift due to packaging and will compensate for it. Very high trim accuracies can be achieved this way.
Despite its high end-accuracy, there are two main disadvantages associated with post-package trim. The first disadvantage of post-package trim is the need for some sort of on-die non-volatile memory. Most process technologies used for fabricating operational amplifiers do not offer non-volatile memory, and if they do, bit cells tend to be not very area-efficient.
The second disadvantage is the need to offer means to externally control the trim state and store the offset compensation value. In many cases this will require the addition of pins to the package, and increase cost. Alternatively, the part can employ some sophisticated multiplex approach to reuse the existing pins for controlling the offset trim algorithm. Such setup requires complex circuitry, however, adding to the die size and cost.
An approach to post-package trim that does not require non-volatile memory and external control of the trim algorithm is so-called power-on calibration. Using this technique, the part is not trimmed during manufacturing, but instead each time the part is powered up (see “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”, C. C. Enz and G. C. Temes, IEEE J. Solid-State Circuits, vol. 84, November 1996, pp. 1584-1614 and “A high-performance autozeroed CMOS opamp with 50 μV offset”, Krummenacher et al., Solid-State Circuits Conference, 1997, Digest of Technical Papers, pp. 350-351, 483). Since the stored offset compensation value needs to be retained only while the supply power is available, power-on calibration alleviates the need for non-volatile memory. Instead, volatile memory can be used. This type of memory offers small die size, and it is ubiquitously available in any CMOS process technology in the form of flip-flops.
FIG. 1 shows the block diagram of an amplifier with power-on calibration.
It uses the successive approximation algorithm to cancel out the random input referred offset voltage Vos. Offset calibration of amplifier A is achieved through switch S, comparator COMP, the successive approximation state-machine SAR and finally the digital-to-analog converter D/A that feeds an offset correction voltage to amplifier A. When the amplifier is powered on, switch S is closed. This forces a differential input voltage that is equal to the input referred offset voltage Vos at the input of amplifier A. Since there is no feedback, the amplifier A operates in the comparator mode: if the differential input voltage is greater than zero, its output will jump to the positive rail, and vice verse (assuming the offset correction voltage at port N is zero).
FIG. 2 shows a simplified representation of the amplifier circuit in FIG. 1 during calibration.
While calibrating, the input switch in FIG. 1 connects the offset source Vos between the two differential inputs of amplifier A. This is represented by the offset source Vos in FIG. 2. Since the D/A output voltage Vda drives offset compensation port N on amplifier A1 in FIG. 1, the effect of Vda can be thought of as being subtracted from the offset voltage Vos at the input of the amplifier. This is indicated in FIG. 2 by the plus sign for the voltage Vos, and the minus sign for the voltage Vda. The difference between offset voltage Vos and correction voltage Vda is error voltage ε. The sign of the error voltage ε, through amplifier A and comparator COMP, drives the decisions of the successive approximation algorithm.
After power-up the circuit will start its successive approximation state-machine to find a value for the offset correction voltage Vda at the secondary input N that minimizes the input referred offset voltage of the overall circuit. The successive approximation operates as follows (see Analog-To-Digital and Digital-To-Analog Converters, R. J. van de Plassche, Springer, 1994). The circuit starts off with all bits to the digital-to-analog converter D/A set to zero. This causes the most negative voltage Vda to be set on the offset compensation input N. If the offset compensation range is large enough, this negative voltage will always cause the output of amplifier A to trip high (ε>0). In the next cycle, the most significant bit (MSB or bn) of D/A will be tested high. If this causes the output of A to go low (ε<0), the bit will be returned to its low state before proceeding to the next bit. Otherwise, if the output of A does not change due to setting the MSB (ε>0), the bit will remain high. The state of the MSB will be stored into a register and does not change during the remainder of the calibration process. In the following step, the bit below the MSB (bn−1) will be tested high and the resulting bit value stored into the register. This process continues successively through all bits, high to low, until the least significant bit is tested and its value stored.
Table 1 shows an example of the offset calibration procedure for a 3-bits SAR register in the simple case that the offset voltage Vos, is zero.
TABLE 1Example of the successive approximation algorithm,assuming Vos = 0ε [V]b3b2b1Vda(Vos −Step(±1 V)(±0.5 V)(±0.25 V)[V]Vda)Comment0000−1.75+1.75Initial State1100+0.25−0.25ε < 0, b2 = 02010−0.75+0.75ε > 0, b1 = 13011−0.25+0.25ε > 0, b0 = 14011−0.25+0.25Final State
The table assumes that the MSB b3 switches between the values −1V (bit low) and +1V (bit high). The other bits are binary weighted, such that b2=±0.5V and b1=±0.25V. Bits tested by the algorithm are underlined. The error value ε in the example of Table 1 approaches zero within the step size of one LSB (0.5V). The resulting binary code is (011) (see the bottom row).
Table 2 gives a similar example of the successive approximation algorithm, now assuming that the input offset voltage Vos is 1.6V. In this case the bits converge to the code (110), with a remaining error ε of 0.35V, which is again within one LSB step size.
TABLE 2Example of the successive approximation algorithm,assuming Vos = 1.6ε [V]b3b2b1Vda(Vos −Step(±1 V)(±0.5 V)(±0.25 V)[V]Vda)Comment0000−1.75+3.35Initial State1100+0.25+1.35ε > 0, b2 = 12110+1.25+0.35ε > 0, b1 = 13111+1.75−0.15ε < 0, b0 = 04110+1.25+0.35Final State
Notice how in the examples in Table 1 and Table 2 the remaining output error ε is always greater than zero. This is a property of the successive approximation algorithm: if a particular bit is tested high and the error voltage ε becomes smaller than zero, the bit is reset to zero. As a result, the algorithm does not allow the error ε to become negative.
In fact, the distribution of the error ε is between zero and one LSB step size Slsb. Ideally, we would like to see the error centered around zero. Doing so will half the maximum error ε from +1 Slsb to ±½ Slsb. In order to perform the re-centering, we will need to add a value equal to ½ Slsb to the D/A converter voltage Vda after the calibration completes. The shift of the final D/A converter voltage Vda can be achieved by adding one more bit to the D/A converter, below the least significant bit b1 (LSB). This additional bit is held at zero during the calibration process, and subsequently set to one, once the calibration is done. Table 3 illustrates the addition of a shift bit to the algorithm.
TABLE 3Example of the successive approximation algorithmwith a shift bit, assuming Vos = 1.6b3b2b1bsVdaε [V]Step(±1 V)(±0.5 V)(±0.25 V)(±0.125 V)[V](Vos − Vda)Comment00000−1.875+3.475Initial State11000+0.125+1.475ε > 0, b2 = 121100+1.125+0.475ε > 0, b1 = 131110+1.625−0.025ε < 0, b0 = 041101+1.375+0.225Final State
In this example, the error ε in the final state is 0.225V (bottom row), which is less than half an LSB step size (0.25V).
Even though the successive approximation algorithm is very powerful in calibrating out the offset of an amplifier at power-up, it suffers from a major drawback. In order for the algorithm to be able to guarantee a certain end-accuracy of the calibration, matching of the various components in the D/A converter needs to be extremely tight. Especially matching of the MSB step size Smsb to the other bits turns out to be critical. The matching error of the MSB step size Smsb must be significantly less than one LSB step size Slsb in order for the mismatch not to affect the overall accuracy appreciably:ΔSmsb<<Slsb  (1)This can be rewritten as
                                                        Δ              ⁢                                                          ⁢                              S                msb                                                    S              msb                                ⁢                      <<                                          S                                  1                  ⁢                                                                          ⁢                  sb                                                            S                msb                                                    =                  1                      2                          n              -              1                                                          (        2        )            where n equals the number of bits of the D/A converter.
Accepting a maximum error due to mismatch of the MSB equal to half an LSB step size ½ Slsb, the expression for the maximum matching error of the MSB simplifies to
                                          Δ            ⁢                                                  ⁢                          S              msb                                            S            msb                          ≤                  2                      -            n                                              (        3        )            
Similar constraints as for the MSB on the maximum matching error occur for the other bits of the A/D converter, albeit with progressively looser matching requirements. The step size of the bits becomes smaller by a factor two for each step when going from the MSB to the LSB. Therefore the expression for the maximum matching error of individual bits becomes
                                          Δ            ⁢                                                  ⁢                          S              b                                            S            b                          ≤                  2                      -            b                                              (        4        )            where b equals the bit number (b=n for the MSB, b=1 for the LSB).
Clearly, matching of the MSB will be the most critical.
To illustrate the effect of mismatch on the transfer function of the D/A converter, FIG. 3 shows an example of the output voltage vs. input code of a 3-bit converter without any mismatch error.
The output steps through all eight possible output values with even step sizes as the input code progresses from (000) through (111). The ideal D/A converter of FIG. 3 can generate any voltage needed to compensate for the offset of the overall amplifier within half an LSB step size (½ Slsb).
FIG. 4 shows the transfer function of the same D/A converter, now assuming a mismatch error that causes the MSB step size to be too large.
Note how the output voltage jumps when the input code goes from (011) to (100). This is because during this transition, the MSB is switched on. Turning on the MSB is supposed to almost make up for all other bits switching off, leaving a positive difference of 1 LSB step size Slsb between the output levels for codes (011) and (100). Since in this example the MSB step size Smsb is too large, the MSB over-compensates for the other bits switching off, causing the difference between the two levels to be too large. This creates a gap between the output voltage levels for input codes (011) and (100).
The hatched area is a range of output voltages that is not covered by the D/A converter. If the voltage Vda that is needed to compensate for the offset of the overall amplifier falls somewhere in the middle of the hatched voltage range, the offset voltage most likely cannot be corrected for within half an LSB step size, or ½ Slsb.
When matching errors cause the MSB step size Smsb to be too small, we obtain a D/A response similar to FIG. 5. The transfer function is not monotonic anymore and has a slightly reduced dynamic range compared to the ideal case of FIG. 3.
Despite these two factors, all output voltages within the dynamic range of the converter can now be produced within half an LSB step size (½ Slsb). In other words, despite the MSB mismatch error, we can continue to guarantee that any offset voltage of the overall amplifier can be compensated for within ½ Slsb. Note that monotonicity of the D/A transfer function is not required for the successive approximation algorithm to function properly.
Summarizing the effects of MSB mismatch on the successive approximation algorithm, we find the following:
1. A mismatch error that causes the MSB to be too large will deteriorate the worst-case offset voltage of the overall amplifier after calibration.
2. A mismatch error that causes the MSB to be too small does not significantly affect the overall accuracy of the offset calibration.
FIG. 6 illustrates this conclusion.
On the x-axis, it shows the ratio between the value of the MSB bn and the next bit bn−1 (bit ratio ρ), while the y-axis represents the probability of a certain bit ratio ρ.
Ideally, the bit ratio ρ is 2 (MSB bn twice as large as the next bit bn−1). Due to mismatch between the components used to manufacture the circuit, the actual bit ratio ρ will vary around the mean value of 2 with a normal distribution having standard deviation σρ. In order to make sure that the overall error due to component mismatches does not exceed half an LSB step size (½ Slsb), the bit ratio ρ should not be too large.
The relation between the error Δρ of the bit ratio ρ and the mismatch ΔSn/Sn of the MSB step size can be found as follows
                                          S            n                    =                      2            ·                          S                              n                -                1                                                    ⁢                                  ⁢                                            S              n                        +                          Δ              ⁢                                                          ⁢                              S                n                                              =                                                                      (                                      2                    +                    Δρ                                    )                                ·                                  S                                      n                    -                    1                                                              ⇒                                                          ⁢                                                Δ                  ⁢                                                                          ⁢                                      S                    n                                                                    S                  n                                                      =                                                            Δ                  ⁢                                                                          ⁢                                      ρ                    ·                                          S                                              n                        -                        1                                                                                                              S                  n                                            =                              Δρ                2                                                                        (        5        )            
Using Eq. 3 and Eq. 5, we can now find for the maximum allowed error Δρmax Δρmax=2·2−n  (6)
From Eq. 6 we can find the expression for the maximum acceptable absolute value of the bit ratio ρmax ρmax= ρ+Δρmax=2+21−n  (7)where ρ is the mean or targeted bit ratio
The hatched area in FIG. 6 indicates the forbidden range of bit ratios ρ. Values of the bit ratio ρ that lie above 2+21−n, indicated by the dashed line, lead to the calibration of the overall circuit potentially being out of spec (point 1 above), whereas any value of the bit ratio ρ below this limit guarantees a calibrated offset within the specifications (see point 2 above).
Based on Eq. 7, we can determine the maximum matching error of the bit ratio
                                          Δ            ⁢                                                  ⁢                          ρ              max                                            ρ            _                          =                  2                      -            n                                              (        8        )            
Note how the maximum acceptable matching error Δρmax/ ρ goes down exponentially with the number of bits. Especially with high bit counts, this can result in very tight matching requirements.
Considering n=10 bits as an example, the maximum allowable mismatch error of the bit ratio Δρmax/ ρ equals 2−10, or about 0.1% (Eq. 8). Requiring this to be a 6σ limit (probability of exceeding the spec limit smaller than ˜1 ppb, assuming a normal distribution), means the standard deviation of the MSB bit ratio matching σρ must be smaller than 0.016%.
The matching requirements that follow from Eq. 8 are often very hard—if not impossible—to achieve in practical monolithically integrated circuits. Therefore, current state-of the art amplifiers with power-on calibration rely heavily on production screening of all possible D/A output levels to guarantee that the input referred offset will be within specs across wide ranges of operating conditions. Due to the large number of possible output levels (1024 for n=10), this production screening is both time-consuming and costly.